Analysis of Variation in On-Chip Waveguide

Recently, optical interconnect has emerged as a possible alternative to electrical interconnect at chip-to-chip and on-chip length scales because of its potential to overcome power, delay, and bandwidth limitations of traditional electrical interconnect. This thesis examines the issues of variation involved in the implementation of a robust on-chip optical signal distribution network. First, the variation within the on-chip waveguide network is analyzed in terms of susceptibility to lithographic uncertainties and refractive index variations. Then, the robustness of an ultrashort pulse-based receiver circuit architecture is analyzed. Some variation sources considered are optical input power variation, load capacitance variation, parasitic capacitive coupling, and power supply noise. Simulation results show that, for both the passive waveguide network and the optical receiver circuit, variation can result in clock skew and jitter, which limit the frequencies at which the distribution network can operate. The impact of technology scaling on the optical receiver circuit architecture is assessed with respect to variation. The robustness of the optical network is compared with that of an all-electrical signal distribution network. Results indicate, for the optical signal distribution network, that a trade-off exists between power consumption and robustness towards most sources of variation. In addition, the ultrashort pulse-based receiver circuit design demonstrates robustness towards many variation sources in the presence of technology scaling. The existence of variation in reasonable amounts will not obstruct the functionality of the receiver circuit. However, additional measures must be taken to minimize power supply variation and parasitic capacitive coupling, which will have a greater impact on robustness in future technology nodes. Thesis Supervisor: Duane S. Boning Title: Professor of Electrical Engineering and Computer Science